Field of the Invention
This invention relates to a semiconductor device, in particular, a semiconductor device that has a plurality of memory cell arrays.
Description of the Related Art
In a semiconductor device, such as DRAM (Dynamic Random Access Memory), a memory cell array is divided into multiple regions and data input/output terminals, data buses, etc., are arranged between the divided memory cell array regions in many cases (see patent document 1).                [Patent document 1] Japanese Laid-Open Patent Publication No. 8-139287        
However, some methods of assigning memory cell array regions and data buses and of laying out data buses pose various problems, such as a shift in data input/output timing between memory cell array regions, an increase in the number of necessary shield lines, and a change in data input/output timing depending on operation modes.
In one embodiment, there is provided a device that includes a memory cell array including a plurality of memory cells, a data node coupled to transfer data from/to a selected one of the plurality of memory cells, a first data terminal, a second data terminal, a first switching buffer coupled between the data node and the first data terminal and a second switching buffer coupled between the data node and the second data terminal. The first switching buffer and the second switching buffer are arranged such that a distance between the first switching buffer and the second data terminal is shorter than a distance between the second switching buffer and the second data terminal and that a distance between the first switching buffer and the first data terminal is shorter than a distance between the second switching buffer and the first data terminal.
In another embodiment, there is provided a device that includes an active area having a square shape divided into first, second, third, fourth, fifth, sixth, seventh, eighth and ninth regions arranged in a matrix, a plurality of memory arrays each including a plurality of memory cells arranged in each of the first, second, third and fourth regions, a plurality of data terminals arranged in the eighth region, a first switching buffer coupled between a data node of one of the memory arrays and one of the data terminals, a second switching buffer coupled between the data node of the one of the memory cell arrays and a different one of the data terminals. The first, second, third and fourth regions are arranged at respective corners of the square. The fifth region is arranged at a center of the matrix. The sixth, seventh, eighth and ninth regions are arranged between the first and second regions, the second and third regions, the third and fourth regions and the fourth and first regions, respectively. The first switching buffer is arranged in the seventh region. The second switching buffer is arranged in the seventh region.
In still another embodiment, there is provided a device that includes a first memory array, a second memory array, a plurality of first data terminals and second data terminals arranged in the first direction between the first memory array and the second memory array, a third memory array arranged such that the first memory array is arranged between the third memory array and the plurality of first data terminals and second data terminals, a fourth memory array arranged such that the second memory array is arranged between the fourth memory array and the plurality of first data terminals and second data terminals and a data bus. The data bus is configured to couple each of the first memory array and the second memory array to the first data terminals in a first operation mode, couple each of the first memory array and the second memory array to the second data terminals in a second operation mode, and couple to the third memory array and the fourth memory array to the second data terminals in each of the first operation mode and the second operation mode.